MCBSTM32EXL【PDF 267/995 页】BOARD EVALUATION FOR STM32F103ZE

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RM0008

13.3.4

Advanced-control timers (TIM1&TIM8)

Clock selection

The counter clock can be provided by the following clock sources:

●

●

●

●

Internal clock (CK_INT)

External clock mode1: external input pin

External clock mode2: external trigger input ETR

Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for

example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Section :

Using one timer as prescaler for another timer on page 353 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1

register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed

only by software (except UG which remains cleared automatically). As soon as the CEN bit

is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 72 shows the behavior of the control circuit and the upcounter in normal mode,

without prescaler.

Figure 72. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register

31

32 33 34 35 36 00 01 02 03 04 05 06 07

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count

at each rising or falling edge on a selected input.

Figure 73. TI2 external clock connection example

TIMx_SMCR

TS[2:0]

ITRx

0xx

or

TI2F

TI1F

or

or

encoder

mode

111

TI2

Filter

TI2F_Rising

Edge

Detector TI2F_Falling

0

1

TI1_ED 100

TI1FP1 101

TI2FP2 110

ETRF

TRGI

ETRF

external clock

mode 1

external clock

mode 2

CK_PSC

ICF[3:0]

TIMx_CCMR1

CC2P

TIMx_CCER

CK_INT

(internal clock)

internal clock

mode

ECE

SMS[2:0]

TIMx_SMCR

Doc ID 13902 Rev 9

267/995

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